Bias PS question

[kagliostro]

I know that this thing was discussed some time ago, but I'm not able to find the thread

This kind of Bias PS is used on JCM900 and discussed and explained on Sluckey's Scrapbook


This image is the correct version

the thing about I'm asking is:

which is the math to find which will be the negative voltage range available ?

Reading Sluckey explanations I know the B+ is halved


can I use the math used in a standad resistor voltage divider to compute the vaslues ?

Thanks

Franco

[2deaf]

You are short one, very critical resistor.

[kagliostro]

I don't know if my math is correct

I used a Voltage Divider calculator and experimented some values, the result is 91Kresistor + 10Kpot + 5.6Kresistor


This image is the correct version

With the wiper of the pot all rotated near the 5.6K resistor Bias voltage will be around 9v

With the wiper of the pot all rotated near the 91K resistor Bias voltage will be around 25v

But I absolutely have no idea if this can correspond to the real world 

Any idea ???

Franco

[jjasilli]

I couldn't attach Sluckey's drawing.  Your missing the 56K shunt resistor.  Sluckey is not showing supply voltage, pot value or bias voltage. I suggest you get those values form a JCM900 schematic, and guesstimate your values from there.

[kagliostro]

Thanks JJasilli, I'll correct the images   


The values on the first version of the schematics are those of Sluckey's Scrapbook (same of the JCM900 I think)

Franco


p.s.: Images corrected

[2deaf]

You will not get -175V DC after the diode.  You will probably get something like -50V.  The load on the bias circuit makes a big difference with the DC voltage after the diode.  In your first drawing, the load goes from 112K to 62K and this change will significantly impact the DC voltage just by itself.  Then the change in the voltage divider will also change the bias, so two factors are affecting the bias voltage at the same time.

[sluckey]

I have never seen any math to calculate the amount of dc available from that circuit. I just build the basic circuit and then experimentally determine the voltage divider resistor values to obtain the desired adjustable voltage range.

I think it's not a coincidence that the X_c for that .047µF cap is 56K at 60Hz, same as the 56K resistor following it. I've thought about this before but it's never been more that a fleeting thought. I have enough knowledge about this circuit to understand how it works, how to successfully build it, and to trouble shoot it if it breaks. I'm not interested enough to really dig deep for more understanding. But I will quietly sit still if someone wants to pour that knowledge into my head.   

[kagliostro]

Ciao Steve

I really don't understand what is happening there

but looking to the oscilloscope images seems to me that we are working on half the B+ value and that 1/2 value

is to be used for the math

But I only suppose because I'm far to understand the whole thing

Franco

[PRR]

IMHO, the math is "impossible".

It clearly "can" be calculated. But the interaction of a C, an R, and a Diode is real complicated.

If at all possible, get a 50VAC tap or even run a 120V:12V backward on a 6VAC supply (gives 60VAC and >80VDC). Simpler and IMHO more reliable.

If you must have the math, try DIYAudio. There are some math wizzes there. Also a bunch of noise-makers who will give wrong answers or tell you you are doing it all wrong.

[silverfox]

IMHO, the math is "impossible".

It clearly "can" be calculated. But the interaction of a C, an R, and a Diode is real complicated.

If at all possible, get a 50VAC tap or even run a 120V:12V backward on a 6VAC supply (gives 60VAC and >80VDC). Simpler and IMHO more reliable.

If you must have the math, try DIYAudio. There are some math wizzes there. Also a bunch of noise-makers who will give wrong answers or tell you you are doing it all wrong.

I asked an electronics instructor similar questions regarding calculations of the bias with that RC diode network and he said the same thing as you PRR. I got close and got it to work but it required a lot of experimenting. Something that caused much headache was starting out with a 4 bias feed design. when I added the 3rd and 4th feeds to the basic supply circuit the load impedance changed and required a different minimum load resistor. Then the adjustment pots interacted and the whole circuit would go heywire. I know you're not using multiple bias ports, just sayin.

silverfox.

[kagliostro]

Thanks for the suggestion PRR

I agree, with a separated winding all will be simple

the simpler way to use the JCM900 Bias circuit modified to achieve the desired output

will be to mount the components and test various values (may be initially using all pot instead of resistors and pot)

Thanks also to you Silverfox

Franco

[HotBluePlates]

... I think it's not a coincidence that the X_c for that .047µF cap is 56K at 60Hz, same as the 56K resistor following it. ...

... but looking to the oscilloscope images seems to me that we are working on half the B+ value and that 1/2 value ...

As Steve noted, the 0.047µF cap and the 56kΩ resistor form an a.c. voltage divider, with each component looking like ~56kΩ at 60Hz.  So the input to the diode is 1/2 of the secondary voltage, as Franco measured.

IMHO, the math is "impossible".

It clearly "can" be calculated. But the interaction of a C, an R, and a Diode is real complicated.

...  The load on the bias circuit makes a big difference with the DC voltage after the diode.  ...

The resistances to ground (pot + series resistor) are the load on this circuit.  If they weren't there, the output voltage could be as high as 250vac / 2 = 125vac  -->  125vac * 1.414 = ~177vdc.

So the output voltage is something between -177vdc and 0v.  The 91kΩ against the ~16kΩ (10kΩ pot + 5.6kΩ resistor) to knock this voltage down.  So now maybe something between -177vdc * [16kΩ/(91kΩ+16kΩ)] = ~26vdc and 0v.  If you make the 91kΩ (of your 2nd drawing) smaller and/or the 16kΩ bigger, the negative voltage will be greater.

The math is a pain because you're looking for the average value of a half-wave rectified sine wave.  (Bias Filter) Capacitor value and resistive load alter the average output of the rectifier circuit.  RDH4 didn't even try to give a formula for the result of this, they gave a chapter with at least 6 graphs to use to determine the output voltage.  Which is why PRR mentions the "math is impossible".  That's because the answer is the result of many steps.

The above is also why I have objected to a simplified chart for output voltage of rectifier tubes; it is the exact same problem with the same complications, and the only definite answer is the highest-possible output voltage.

[kagliostro]

Thanks for the answer HotBluePlates

Now I'm going to sleep because my brain say me to do that


Tomorrow morning I'll read with attention your post (excuse me if I don't do it now), tomorrow I'll post the answer that an italian friend of a forum gived me just a pair of minutes ago, it seems very interesting and may be the solution to the problem


Good Night (I'm really asleep)


Franco

[sluckey]

Merlin Blencowe - Designing Power Supplies for Valve Amplifiers- page 183-184 has an interesting discussion on this circuit. No math though.

[jjasilli]

Where is sluckey's scapbook?  I seem to have an old version saved to disc.

[shooter]

you're looking for the average value of a half-wave rectified sine wave.

If this was a "pure DC" circuit,(say <10mVAC), that makes the math just volts dropped across R's?

[sluckey]

Where is sluckey's scapbook?  I seem to have an old version saved to disc.

Here it is. Page 6 has this circuit...

http://sluckeyamps.com/misc/Amp_Scrapbook.pdf

[jjasilli]

 

[2deaf]

As Steve noted, the 0.047µF cap and the 56kΩ resistor form an a.c. voltage divider, with each component looking like ~56kΩ at 60Hz.  So the input to the diode is 1/2 of the secondary voltage, as Franco measured.

The peak-to-peak voltage will increase if you increase R beyond 56K and the peak-to-peak will decrease if you decrease R.  However, it is not at 1/2 of the secondary voltage at R=56K with a 100K load.  You might be able to get it down to 1/2 the secondary voltage by dramatically reducing the load resistance, but that would also dramatically reduce the bias absolute value (the bias magnitudes shall hereinafter be absolute values).  Increasing the input resistor can actually cause the input peak-to-peak voltage to exceed the secondary voltage.

None of this really matters, because it is only the negative portion of the input signal to the diode that determines the resulting bias voltage.  The negative portion doesn't change very much compared to the peak-to-peak when you alter the input resistor, so a wide range of resistance will yield about the same bias.  If you alter the load resistor, there is a much more profound change in the negative portion while the positive portion remains about the same.

The maximum bias voltage with a 100K load will occur with an input resistor somewhere between 47K and 56K.  The bias voltage will decrease on both sides of this input resistance in a non-linear fashion.

The resistances to ground (pot + series resistor) are the load on this circuit.  If they weren't there, the output voltage could be as high as 250vac / 2 = 125vac  -->  125vac * 1.414 = ~177vdc.

Even when unloaded, the negative portion of the diode input signal is less than the positive portion and less that 1/2 of the peak secondary voltage.  The asymmetry of the input signal becomes less as you increase the load resistance, but it never becomes symmetric even with an infinite load resistance.

So the output voltage is something between -177vdc and 0v.  The 91kΩ against the ~16kΩ (10kΩ pot + 5.6kΩ resistor) to knock this voltage down.  So now maybe something between -177vdc * [16kΩ/(91kΩ+16kΩ)] = ~26vdc and 0v.  If you make the 91kΩ (of your 2nd drawing) smaller and/or the 16kΩ bigger, the negative voltage will be greater.

Sluckey is showing -52V with no voltage divider, so you are unlikely to have -26V with a large divider like that.



   

[2deaf]

It clearly "can" be calculated. But the interaction of a C, an R, and a Diode is real complicated.

It gets even more complicated with two R's.

[2deaf]

I think it's not a coincidence that the X_c for that .047µF cap is 56K at 60Hz, same as the 56K resistor following it.

If you use a .022uF input capacitor instead of a .047uF, the peak bias is with an input resistor of around 82K.

[kagliostro]

Many thanks to ALL

HotBluePlates gived a very good explanation

Yesterday I was saying I had an answer to this thing in an italian forum

Substantially this kind of PS is similar to a transformerless power supply

this type of power supplies have the characteristic to take advantage of the capacitive reactance of a capacitor to reduce the voltage to the desired levels

here there is a good documentation (unfortunately only in italian)

http://www.electroyou.it/powermos/wiki/transformerless

But if you are interested you can find english docomentation on this book

Nathan O. Sokal, K. Kit Sum, David C. Hamill, "A Capacitor-Fed, Voltage-Step-Down, Single-Phase, Non-Isolated Rectifier", APEC 1998, Volume 1, Issue , 15-19 Feb 1998 Page(s):208 - 215 vol.1

and on this .pdf

http://ww1.microchip.com/downloads/en/AppNotes/00954A.pdf

Here is the schematic that was posted with the explanation on the answer to my question

Leaving aside the section of circuit that generates the anode voltage (+ 340V), the circuit that generates the bias voltage is the following:



The capacitor at mains frequency (50Hz) offers a capacitance of about 68K (XC = 1/6,28 * f * C)

With positive half wave on node A diode D1 is reverse biased and does not pass current. The voltage at node B is given by the divider formed by XC and R1

With negative half-wave on node A, the diode D1 is forward biased and the voltage at node B, if one neglects the Vf drop of the diode, is given by the divider formed by XC and R1// ( R2 + R3 + R4)

Attention because, in turn, R3 and R4 have the load in parallel connected to Bias, however,  is that if it is the grid of a thermionic valve should be a negligible current

So what HotBluePlates and Sluckey told is further confirmed

An insane idea come to me, but I don't think I want to realize  also if it is feasible 



(Note that this way the negative voltage will be doubled respect B+)


Many thanks again friends

Franco

[DummyLoad]

franco - use a transformer. 

[kagliostro]

Thanks DummyLoad

That will be very simply

but I think that now I can use the JCM900 schematic being able to arrive around the voltage I want on the paper

and then adjusting the resistors

For sure I don't want to go with a bridge that way

Effectively a transformer will simplify things, but require space

This thing was a study on the matter, for a pair of a bit unusual idea I've

Ciao

Franco

[2deaf]

Here is the schematic that was posted with the explanation on the answer to my question

Leaving aside the section of circuit that generates the anode voltage (+ 340V), the circuit that generates the bias voltage is the following:

You cannot leave aside the section of the circuit that generates the B+ voltage because the AC path for the bias circuit flows through the B+ capacitor(s).  The bias circuit you posted will not yield any voltage at all by itself because the path is blocked in both directions.

It might be instructive to look at the JCM900 with the standby open.  In this mode, there is no complete B+ circuit and the bias AC circuit still goes through the B+ capacitors (in fact, it is the only thing going through the B+ capacitors).  Now you clearly have a half-wave power supply with ground referenced to the junction of two capacitors in series which will give a lower voltage at the bias point relative to ground than if you had connected ground to the bridge end of the series capacitors.  Now you have a nice symmetrical AC signal with positive and negative sides going into your RC input network and a much nicer signal for the diode to rectify.  The bias voltage will be much higher (still absolute values) with the standby open than with it closed.  Perhaps this is the situation that you guys are referring to.  When you close the standby, everything radically changes.  This is the situation I am referring to.   

[kagliostro]

Ciao 2deaf

That schematic was only an example draw that way to semplify the view

of course the B+ part of the whole PS must be build

Franco

[Ed_Chambley]

Why would you need this method?  Just curious.  If I do not have a bias tap, I simply use the HT.


Does this bias method have a special purpose?

[kagliostro]

That method is for PT without a CT


Franco

[Ed_Chambley]

That method is for PT without a CT


Franco

Thanks, this a good thing to know. I knew you had some application you were using it for.  I can use this for toroidaltransformers with fixed bias.